This invention relates, in general, to semiconductor devices, and more particularly, but not limited to, a method of forming isolated P-type wells in the fabrication of BiCMOS structures.
A BiCMOS circuit integrates complementary MOS transistors, as well as complementary bipolar transistors. With the integration of more and more multiple functions onto a single chip, signal isolation between devices has been reduced. Particularly when both analog and digital devices are integrated onto the same chip, crosstalk can be a major problem. In the past, only the N-type well of the NPN and PMOS is typically isolated from the substrate. Thus, crosstalk can occur because the NMOS and vertical PNP transistors are fabricated in a common substrate. This common substrate prevents independent biasing of the NMOS backgate and the vertical PNP collector and allows for noise coupling between transistors, which is undesirable.
Thus, a need has arisen for a method of improving signal isolation by isolating the P-type wells as well as the N-type wells from the substrate. This method should be compatible with existing BiCMOS technology and applicable to high performance devices. The isolation of the P-type well would also allow for separate back gate bias for NMOS devices, as well as isolation of the memory cells for SRAMs.
In the past, a standard N+ buried layer has been used. The use of this standard N+ buried layer requires the use of a thick epitaxial layer in which the active device is fabricated and thus, is only adequate for low performance BiCMOS technology (having an NPN transistor with a maximum frequency less than 3 gigahertz and a gate delay of greater than or equal to 500 picoseconds). High performance BiCMOS requires the use of a thin epitaxial layer. A standard N+ buried layer cannot be used for isolated NMOS or PNP fabricated in a thin epitaxial layer because the N+ buried layer would come too close to the source/drain of the device fabricated in the P-type well. If the N+ buried layer is too close to the active junctions of the device, punch-through and leakage preclude useful circuit operation.
Another method which has been used to isolate P-type wells is an N- buried layer (or well). However, the use of an N- buried layer is not adequate for forming high density BiCMOS circuits, because the long heat cycle necessary to diffuse the N- buried layer deep into the substrate results in excessive lateral diffusion and low device packing density. In addition, extra processing is required to align the N- buried layer to the N+ buried layer 11' (used in the PMOS and NPN), thus increasing process complexity and lowering yield.
Thus, there is a need to form isolated P-wells for the fabrication of high performance BiCMOS while minimizing process complexity and cost.